1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory device and, more specifically, to a dynamic type semiconductor memory device in which the number of circuit elements in an error correcting circuit is reduced.
2. Description of the Background Art
FIG. 1 is a block diagram showing a conventional dynamic type semiconductor memory device (DRAM) having an error correcting circuit.
The structure will be described with reference to the figures.
A memory cell array is divided into two regions, that is, a data cell array 1 storing data information and a parity cell array 2 for checking errors. The peripheral circuits of the memory cell array are: an address buffer 3 for receiving external row address signals and column address signals; a row decoder 4 and a column decoder 5 for applying voltages to word lines and bit lines for designating a specified memory cell by decoding these address signals A.sub.i transmitted through address buses; a sense amplifier 6 for amplifying and reading the signals stored in the memory cell designated by these two decoders; a control clock circuit 7 for receiving external control signals to apply the same to respective portions; an I/O buffer 8 connected to the outside for writing/reading information transmitted through an I/O bus; an error checking.multidot.correcting (ECC) control circuit 9 for receiving a signal from the control clock circuit 7 to generate signals for activating an error correcting circuit; a transmission type exclusive OR circuit 10 for calculating a syndrome, which is one of the error correcting circuit; a data correcting circuit 11 for correcting errors, if any, to provide corrected data; a driver 12 for transmitting a syndrome generated by the transmission type XOR 10 to a syndrome decoder 13; and a syndrome decoder 13 for decoding the generated syndrome.
FIG. 2 is a portion of a circuit diagram of a memory cell array having 64 rows and 64 columns in a conventional dynamic semiconductor memory disclosed in, for example, Japanese Patent Laying-Open Gazette No. 74535/1976, which is referred to for illustrating the operation of the memory cell array of FIG. 1.
The structure will be described in the following with reference to the figure.
A plurality of memory cells MC.sub.0,0, MC.sub.0,1, MC.sub.0,2, MC.sub.0,3 . . . and dummy cells DM.sub.0,0 and DM.sub.0,1 are connected to each of a pair of bit lines BL.sub.0 and BL.sub.0. The memory cell MC.sub.0,0 comprises an NMOS transistor Q and a capacitance C.sub.S. Each of the memory cells and the dummy cells has the same structure. Word lines W.sub.0, W.sub.1, W.sub.2, W.sub.3 . . . arranged orthogonal to the bit line pair are connected to the gates of the transistors constituting the memory cells. Dummy word lines DW.sub.0 and DW.sub.1 arranged orthogonal to the bit line pair are connected to the gates of the transistors constituting the dummy cells. The word lines and the dummy word lines are connected to a row decoder 4. A sense amplifier SA.sub.0 is connected to end portions of the bit line pair. The sense amplifier SA.sub.0 comprises PMOS transistors 1 and 2 and NMOS transistors 3 and 4, with sense amplifier activating signals SP and SN connected to each of these transistors. The sense amplifier activating signals SP and SN are generated from a sense signal generating circuit SSG. End portions of the bit line pair BL.sub.0 and BL.sub.0 are connected to input/output lines I/O and I/O through NMOS transistors 35 and 36. A Y signal line Y.sub.0 drawn out of the column decoder 5 is connected to the gates of the transistors 35 and 36. Other bit line pairs have the same structure. The input/output lines I/O and I/O are respectively connected to a data output main amplifier MA and a data input buffer DIB to exchange information with the outside, the data output main amplifier MA and the data input buffer DIB constituting a pair to form an I/O buffer 8.
The operation will be described in the following.
Let us assume that the memory cell MC.sub.0,0 is selected in a reading cycle. At that time, the row decoder 4 raises potentials of the word line W.sub.0 and the dummy word line DW.sub.0, and electric charges which have been stored in respective memory capacitances of the bit line pairs BL.sub.0, BL.sub.0 to BL.sub.63, BL.sub.63 previously charged to equal potentials are transferred through respective transistors Q. For example, the charges representing information of the memory cell MC.sub.0,0 are transferred to the line BL.sub.0, and the charges of the dummy cell DM.sub.0,0 are transferred to the bit line BL.sub.0 so as to generate a reference voltage. Thereafter, the sense amplifier activating signal SN becomes low level and the sense amplifier activating signal SP becomes high level, whereby sense amplifiers SA.sub.0 to SA.sub.63 are activated. Namely, small differences between signal voltages appeared on each of the bit line pairs by the charges representing information transferred to the bit line pairs are sensed and amplified.
Thereafter, the column decoder 5 selects the Y signal line Y.sub.0 in accordance with a column address externally applied, whereby the transistors 35 and 36 are turned on. Complementary signal voltages on the bit line pair BL.sub.0 and BL.sub.0 are respectively transferred to the I/O bus line pair I/O and I/O, amplified by the data output main amplifier MA to be externally outputted as an output data D0. In the writing cycle, data are written into a desired memory cell through reverse operation to the reading cycle. Namely, the level of an input data DI applied from outside of the chip is converted by the data input buffer circuit DIB to be complementary signals, and the signals are transferred to the I/O bus line pair I/O and I/O. The complementary input data on the I/O bus line pair are transferred to the bit line pair BL.sub.0 and BL.sub.0 by the selection of the Y signal line Y.sub.0 by the column decoder 5. The charges representing information are written in the memory cell MC.sub.0,0 which is at the intersection of the word line W.sub.0 selected on that occasion.
FIG. 3 is a block diagram of a semiconductor memory device having an error checking and correcting function employing Hamming codes, comprising a transmission type exclusive OR circuit disclosed in Conf. IEICE Japan, Conf. Rec., March 1986, pt. 2, pp. 2-244 for illustrating the operation of the error correcting circuit of FIG. 1.
FIG. 4 is a schematic diagram of an input/output line 15, a column decoder 5, an input/output gate portion 14, memory cell arrays 1, 2, bit lines BL and a word line WL shown in FIG. 3.
The operation will be described in the following with reference to these figures.
The operation of each portion in writing data in a memory cell 1a will be described as an example. When (0, 0, 0, 0) are inputted as the address signals A.sub.0 to A.sub.3, a transistor 2a in the input/output gate portion 14 connected to the memory cell 1a is selected by the column decoder 5, and the transistor becomes conductive. At the same time, the word line WL in the memory cell array 1 is driven to select the memory cell 1a. The data inputted through the input/output line 15 is written in the memory cell 1a through the transistor 2a. In reading, the data is outputted from the input/output line 15 through the reverse path. The memory cells 1a to 1p hold 16 bits of information bit data (X.sub.1 . . . X.sub.16) and the memory cells 1q to 1u hold 5 bits of check bit data (C.sub.1 . . . C.sub.5), respectively.
The memory cells constitute a code word C having the following parity check matrix H with the number of information bits being 16 and the number of check bits being 5. ##EQU1##
The parity check matrix H is defined by the transmission type exclusive OR circuit 10 connected in the succeeding stage. The check bit data (C.sub.1 . . . C.sub.5) are previously set to satisfy the following equation in association with the information bit data (X.sub.1 . . . X.sub.16). ##EQU2##
A syndrome S is defined by the parity check matrix H and the code word C in the following equation. ##EQU3##
The checking of data will be described in the following. When there is no error in each data of the code word C comprising 16 bits of information bit data (X.sub.1 . . . X.sub.16) and 5 bits of check bit data (C.sub.1 . . . C.sub.5), the syndrome S for the parity check matrix H becomes 0 as represented by the equation (2), whereby it is confirmed that the held data are correct.
When a first bit X.sub.1 is erroneously inverted, the syndrome S.sub.el of the code word C.sub.el having the erroneous data will be not 0 but S.sub.el.sup.T=H.multidot.C.sub.el.sup.T=( 1, 1, 0, 0, 0).sup.T, which is the same as the vector of the first column of the parity check matrix H shown in (1). In the similar manner, when the i th bit is erroneously inverted, the syndrome S.sub.ei for the code word C.sub.ei will be the same as the vector of the i th column of the parity check matrix H. Whether there is an error in the data or not, and if any, which data is the erroneous one can be checked by calculating the syndrome S of the code word C. The syndrome S is calculated in the transmission type exclusive OR circuit 10 in the succeeding stage.
FIG. 5 is a schematic diagram of the transmission type exclusive OR circuit shown in FIG. 3. The syndrome signals S.sub.1 to S.sub.5 are calculated by the combination of the exclusive OR of the information bit data (X.sub.1 . . . X.sub.16) and the check bit data (C.sub.1 . . . C.sub.5). The transmission type exclusive OR circuit 10 is adapted to satisfy the following equations (4) to (8) EQU X.sub.1 .sym.X.sub.2 .sym.X.sub.4 .sym.X.sub.5 .sym.X.sub.7 .sym.X.sub.9 .sym.X.sub.11 .sym.X.sub.12 .sym.X.sub.14 .sym.X.sub.16 .sym.C.sub.1 =S.sub.1 ( 4) EQU X.sub.1 .sym.X.sub.3 .sym.X.sub.4 .sym.X.sub.6 .sym.X.sub.7 .sym.X.sub.10 .sym.X.sub.11 .sym.X.sub.13 .sym.X.sub.14 .sym.C.sub.2 =S.sub.2( 5) EQU X.sub.2 .sym.X.sub.3 .sym.X.sub.4 .sym.X.sub.8 .sym.X.sub.10 .sym.X.sub.11 .sym.X.sub.15 .sym.X.sub.16 .sym.C.sub.3 =S.sub.3 ( 6) EQU X.sub.5 .sym.X.sub.6 .sym.X.sub.7 .sym.X.sub.8 .sym.X.sub.9 .sym.X.sub.10 .sym.X.sub.11 .sym.C.sub.4 =S.sub.4 ( 7) EQU X.sub.12 .sym.X.sub.13 .sym.X.sub.14 .sym.X.sub.15 .sym.X.sub.16 .sym.C.sub.5 =S.sub.5 ( 8)
The error checking and correcting operation will be described in the following. Referring to FIG. 3, the syndrome signals S.sub.1 to S.sub.5 are inputted to a buffer circuit 16 to be amplified therein. When the control input .phi..sub.S is set at "H", the transistors in the syndrome gates 17 become conductive, and the syndrome signals S.sub.1 to S.sub.5 are inputted to the syndrome decoder 13. The syndrome decoder 13 checks whether there is any error in the data, and if any, which of the memory cells contain the erroneous data, in accordance with the bit patterns of the syndrome signals S.sub.1 to S.sub.5. When there is any error in the data, the syndrome decoder 13 selects a transistor (not shown) in an inversion circuit gate 11 connected to the bit line BL of the memory cell which hold the erroneous data. The selected transistor becomes conductive and connects the memory cell holding the erroneous data to the inversion circuit 20A.
The erroneous data is inverted in the inversion circuit 20a to be a correct data. The data is rewritten in the corresponding memory cell through the corresponding transistor (not shown) in the inversion circuit gate 11 and through the corresponding bit line BL.
The rewriting of the check bit data will be describe in the following. When rewriting of the information bit data and so on is carried out, the check bit data (C.sub.1 . . . C.sub.5) must be updated to satisfy the above mentioned equation (2). The check bit data (C.sub.1 . . . C.sub.5) defined by the correct data and which satisfy the equation (2) are formed in inversion circuits 20q to 20u. The correct check bit data (C.sub.1 . . . C.sub.5) are written in memory cells I.sub.q to I.sub.u through corresponding bit lines BL.
The relation between the address signals A.sub.0 to A.sub.3 and the corresponding memory cells 1a to 1p and the relation between the syndrome signals S.sub.1 to S.sub.5 and the corresponding memory cells 1a to 1u holding erroneous data in the above described structure are shown in Table 1.
TABLE 1 ______________________________________ Memory Cell A.sub.0 A.sub.1 A.sub.2 A.sub.3 S.sub.1 S.sub.2 S.sub.3 S.sub.4 S.sub.5 ______________________________________ 1a 0 0 0 0 1 1 0 0 0 1b 1 0 0 0 1 0 1 0 0 1c 0 1 0 0 0 1 1 0 0 1d 1 1 0 0 1 1 1 0 0 1e 0 0 1 0 1 0 0 1 0 1f 1 0 1 0 0 1 0 1 0 1g 0 1 1 0 1 1 0 1 0 1h 1 1 1 0 0 0 1 1 0 1i 0 0 0 1 1 0 1 1 0 1j 1 0 0 1 0 1 1 1 0 1k 0 1 0 1 1 1 1 1 0 1l 1 1 0 1 1 0 0 0 1 1m 0 0 1 1 0 1 0 0 1 1n 1 0 1 1 1 1 0 0 1 1o 0 1 1 1 0 0 1 0 1 1p 1 1 1 1 1 0 1 0 1 1q 1 0 0 0 0 1r 0 1 0 0 0 1s 0 0 1 0 0 1t 0 0 0 1 0 1u 0 0 0 0 1 ______________________________________
The semiconductor memory device having the above structured error correcting circuit is not preferable in improving the degree of integration of the device, since each bit line in each bit line pair must be connected to the exclusive OR circuit 10. Namely, the number of circuit elements for the error checking.multidot.correcting circuit must be equal to the number of bit line pairs in the memory cell array.